Automatic test pattern generation (“ATPG”) was developed to explicitly test each gate and path in an integrated circuit (“IC”) design. As ICs have become larger and more complex, the amount of logic to be tested per input/output test pin has increased dramatically.
When an ATPG tool generates a scan test for a fault, or a set of faults, only a small percentage of scan cells in the scan channels need to take specific values (e.g., care bits). The rest of the cells in the scan channel are “don't care”, and are usually filled with random values. Relatively few bits in an ATPG generated test pattern are “care” bits.
Test Compression takes advantage of the small number of significant values (care bits) to reduce test data and test time. However, as Test Compression decreases channel lengths, the number of specified bits (e.g., care bits) per time slice increases. There can be a large variance in the number of care bits across time slices.
XOR decompressors are also limited in that they are restricted to using only the scan data available in the same scan cycle. This leads to inefficiencies. For example, if the ATPG generated test only requires few care bits in a scan slice, then the rest of the scan data will remain unused.
Sequential decompressors overcome the above-discussed inefficiencies of the XOR decompressors by solving the linear equations of the entire test pattern simultaneously instead of slice-by-slice. Scan data is reused among multiple scan slices, so that scan data from scan slices having fewer care bits can be utilized in solving for scan slices with more care bits. The sequential decompressor network contains a linear feedback shift register (“LFSR”) (also referred to as a Pseudo-Random Pattern Generator—PRPG) that receives data from a plurality of scan input signals and that sends its outputs through a linear spreader network of a plurality of XOR logic gates (e.g., an XOR decompressor). The outputs of the XOR decompressor, fed to scan channels, are a linear combination of the values from the PRPG starting state and the data inputted from a tester into the circuit through scan-input pins. The values outputted from the XOR decompressor lead to linear equations to determine the values to be sent into each scan channels. The PRPG was loaded with scan input variables before any values were shifted into the scan channels. However, this required that the channels be frozen while the scan input variables were being loaded into the PRPG (e.g., by holding the channels' clocks constant), which required an additional test control pin or other internal hardware to achieve.
Accordingly, there is a need for an efficient method of bringing additional variables into the PRPG in the early cycles of the ATPG process without utilizing any additional hardware or control pins.